Regviz

Silicon Labs /Series1 /EFM32GG11B /EFM32GG11B420F2048GQ64 /VDAC0 /CH0CTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CH0CTRL

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Silicon Labs/Series1/EFM32GG11B/EFM32GG11B420F2048GQ64/VDAC0/CH0CTRL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CONVMODE)CONVMODE 0 (SW)TRIGMODE 0 (PRSASYNC)PRSASYNC 0 (PRSCH0)PRSSEL

TRIGMODE=SW, PRSSEL=PRSCH0

Description

Channel 0 Control Register

Fields

CONVMODE

Conversion Mode
TRIGMODE

Channel 0 Trigger Mode

0 (SW): Channel 0 is triggered by CH0DATA or COMBDATA write

1 (PRS): Channel 0 is triggered by PRS input

2 (REFRESH): Channel 0 is triggered by Refresh timer

3 (SWPRS): Channel 0 is triggered by CH0DATA/COMBDATA write or PRS input

4 (SWREFRESH): Channel 0 is triggered by CH0DATA/COMBDATA write or Refresh timer

5 (LESENSE): Channel 0 is triggered by LESENSE
PRSASYNC

Channel 0 PRS Asynchronous Enable
PRSSEL

Channel 0 PRS Trigger Select

0 (PRSCH0): PRS ch 0 triggers a conversion.

1 (PRSCH1): PRS ch 1 triggers a conversion.

2 (PRSCH2): PRS ch 2 triggers a conversion.

3 (PRSCH3): PRS ch 3 triggers a conversion.

4 (PRSCH4): PRS ch 4 triggers a conversion.

5 (PRSCH5): PRS ch 5 triggers a conversion.

6 (PRSCH6): PRS ch 6 triggers a conversion.

7 (PRSCH7): PRS ch 7 triggers a conversion.

8 (PRSCH8): PRS ch 8 triggers a conversion.

9 (PRSCH9): PRS ch 9 triggers a conversion.

10 (PRSCH10): PRS ch 10 triggers a conversion.

11 (PRSCH11): PRS ch 11 triggers a conversion.

12 (PRSCH12): PRS ch 12 triggers a conversion.

13 (PRSCH13): PRS ch 13 triggers a conversion.

14 (PRSCH14): PRS ch 14 triggers a conversion.

15 (PRSCH15): PRS ch 15 triggers a conversion.

16 (PRSCH16): PRS ch 16 triggers a conversion.

17 (PRSCH17): PRS ch 17 triggers a conversion.

18 (PRSCH18): PRS ch 18 triggers a conversion.

19 (PRSCH19): PRS ch 19 triggers a conversion.

20 (PRSCH20): PRS ch 20 triggers a conversion.

21 (PRSCH21): PRS ch 21 triggers a conversion.

22 (PRSCH22): PRS ch 22 triggers a conversion.

23 (PRSCH23): PRS ch 23 triggers a conversion.

Links

()

Register License

  • SPDX-License-Identifier: Zlib
  • The licensor of this software is Silicon Laboratories Inc.
  • This software is provided ‘as-is’, without any express or implied
  • warranty. In no event will the authors be held liable for any damages
  • arising from the use of this software.
  • Permission is granted to anyone to use this software for any purpose,
  • including commercial applications, and to alter it and redistribute it
  • freely, subject to the following restrictions:
    1. The origin of this software must not be misrepresented; you must not
  • claim that you wrote the original software. If you use this software
  • in a product, an acknowledgment in the product documentation would be
  • appreciated but is not required.
    1. Altered source versions must be plainly marked as such, and must not be
  • misrepresented as being the original software.
    1. This notice may not be removed or altered from any source distribution.
 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data